This invention relates to a reference potential generating circuit and a semiconductor memory device having the reference potential generating circuit.
In recent years, a mobile apparatus such as a mobile phone becomes more and more multifunctional and a memory device mounted to the mobile apparatus is increased in capacity. Because the mobile apparatus has a compact size, a semiconductor memory device is used as the memory device for use in the mobile apparatus. For example, in the mobile phone, a flash memory (Flash EEPROM: Flash Electrically Erasable Programmable Read Only Memory) is used as a nonvolatile memory device for storing data such as telephone numbers which are desired to be retained even if a power supply is turned off. Further, as a main memory device, a DRAM (Dynamic Random Access Memory) is used because of its low cost and large capacity. The DRAM mounted to the mobile apparatus is called a mobile DRAM.
Needless to say, power is supplied to the mobile phone during speech communication. Moreover, even when the mobile phone is unused and is ready for call transmission or call reception, a power supply voltage is supplied to the mobile phone and an electric current is consumed. The above-mentioned state where the mobile phone is ready for call transmission or call reception is called a standby state. For the most part of time, the mobile phone is in the standby state ready for call transmission or call reception than in a speech communication state. When the mobile phone is in the standby state, the mobile DRAM requires a refresh operation in order to retain stored data. The stored data of the DRAM is electric charges stored in a capacitance portion of a memory cell. The electric charges stored in the memory cell attenuate with lapse of time and are lost unless rewriting is performed at every predetermined time interval. Therefore, the refresh operation for rewriting the stored data is required. In the standby state which occupies the most part of time in the mobile phone, the electric current is consumed only by the refresh operation. Thus, it is desired to reduce the electric current in the standby state.
The refresh operation in the standby state is automatically performed inside a DRAM circuit without control of a CPU (Central Processing Unit) circuit. Automatic refresh operation inside the DRAM circuit is called a self-refresh operation. In the self-refresh operation, a timer circuit in the DRAM automatically generates a refresh command at every predetermined time interval to continuously activate a word line. A sense amplifier reads data and rewrites the data in the memory cell. As mentioned above, in the standby state of the mobile phone, the refresh operation is performed in the DRAM in order to retain the data stored therein. Therefore, in order to increase an operation time of a battery of the mobile phone, it is very important to reduce the electric current consumed in the refresh operation in the standby state.
The electric current required in the self-refresh operation is a total electric current consumed by generation of the refresh operation at every predetermined time interval. A constant or predetermined electric current is consumed in each single refresh operation. Therefore, the longer a cycle (i.e., the above-mentioned predetermined time interval) of the refresh operation is, the less self-refresh current is required.
A value of the refresh current changes depending on a temperature of the semiconductor memory device. Specifically, a cycle (i.e., the predetermined time interval) in which the above-mentioned timer circuit in the DRAM generates the refresh command, changes with the temperature. As the temperature becomes higher, the cycle is shortened, i.e., the refresh current increases. To the contrary, as the temperature becomes lower, the cycle is lengthened, i.e., the refresh current decreases. For a 512 Mbit DRAM, an actual self-refresh current value is approximately 800 μA at 85° C. and 530 μA at 45° C. Further, for a 256 Mbit DRAM, an actual self-refresh current value is approximately 400 μA at 85° C. and 270 μA at 45° C. For a 128 Mbit DRAM, an actual self-refresh current value is approximately 200 μA at 85° C. and 140 μA at 45° C. Thus, the value of the entire self-refresh current is on the order of several tens to several hundreds microampere.
The self-refresh current includes not only an electric current used in charging and discharging the word line and a bit line as the refresh operation but also an electric current constantly and continuously consumed. The latter electric current is called a through current or a DC current and mostly consumed in a reference potential generating circuit. The reference potential generating circuit is a circuit for generating an internal reference potential, such as a reference potential VDL as a writing voltage of a memory cell array, a precharging reference potential VDL/2, and a sense amplifier operation reference potential VSP/VSN. The DC current consumed in the reference potential generating circuit will be described hereinunder.
The reference potential generating circuit generally comprises a current mirror amplifier, an output transistor, and a monitoring resistance element portion. The current mirror amplifier compares an input reference potential and a feedback level received from the monitoring resistance element portion and makes the output transistor generate an output reference potential. In the reference potential generating circuit, the current mirror amplifier continuously performs comparison and judgment for an input potential. Further, the monitoring resistance element portion is a group of resistors connected between the output reference potential and a ground potential. Therefore, a stationary DC current flows through the current mirror amplifier and the monitoring resistance element portion.
The DC current is characterized in that a substantially-constant current continuously flows, and is therefore independent from the above-mentioned self-refresh cycle. Generally, a plurality of current mirror amplifiers and a plurality of monitoring resistance element portions are present inside the DRAM at a plurality of parts, several to several tens in number. Each part is supplied with an electric current of approximately 3 to 10 μA. Therefore, assuming that an electric current of 4 μA is supplied to each of 15 parts, the DC current of approximately 60 μA in total is required in the entire mobile DRAM. In this case, for the 256 Mbit DRAM, the DC current occupies approximately 22% of the self-refresh current of 270 μA at 45° C. For the 128 Mbit DRAM, the DC current occupies approximately 43% of the self-refresh current of 140 μA at 45° C.
It is understood that, in order to reduce the self-refresh current, the DC current must be reduced also with a priority equivalent to extension of the refresh cycle.
In FIG. 1, a reference potential generating circuit having a two-stage structure is shown as a related art. The reference potential generating circuit has a first-stage reference potential generating circuit supplied with an input reference potential VREF_0 for generating an output reference potential VREF_A and a second-stage reference potential generating circuit supplied with VREF_A as an input reference potential VREF_B for generating an output reference potential VREF_C. The output reference potential VREF_C is used as an input reference potential VREF_D at a next stage. The first-stage reference potential generating circuit has a current mirror amplifier CM11, an output transistor (P-channel transistor) QP11, and resistance elements R11 and R12 constructing a monitoring resistance element portion. A capacitance element C11 retains VREF_A as the input reference potential VREF_B. The second-stage reference potential generating circuit has a current mirror amplifier CM12, an output transistor (P-channel transistor) QP12, and resistance elements R13 and R14 as a monitoring resistance element portion. A capacitance element C12 retains VREF_C as an input reference potential VREF_D at a next stage.
In FIG. 15 of Japanese Unexamined Patent Application Publication (JP-A) No. H10-27026 (Patent Document 1), an internal power supply potential supplying circuit is disclosed. In the internal power supply potential supplying circuit, when a control signal SC1 has an “L” level, a comparator 1 is put into an inactive state to stop an output S1 and a transistor Q4 is turned off (see paragraphs [0104] and [0106] of Patent Document 1).
In the abstract of Japanese Unexamined Patent Application Publication (JP-A) No. H7-105682 (Patent Document 2), a dynamic memory using an internal step-down power supply is disclosed. The dynamic memory is provided with a plurality of (three) internal step-down power supplies. One of the power supplies is always turned on while the other two power supplies are turned off at least in a standby time and turned on in a time period (active time period) except for the standby time.
In FIG. 15 of Japanese Unexamined Patent Application Publication (JP-A) No. H8-190437 (Patent Document 3), an internal power supply voltage generating circuit is disclosed. In the internal power supply voltage generating circuit, n-channel MOS transistors N5 and N6 are connected between a comparison circuit 3 and the ground (VSS) and between a resistance element Z2 and the ground (VSS). The n-channel MOS transistors N5 and N6 are turned into an off state when a period control signal EN has an L level as an inactive state (see paragraphs [0077] and [0075] of Patent Document 3).
As mentioned above, the DC current flows through the current mirror amplifier and the monitoring resistance element portion. The current mirror amplifier and the output transistor perform a negative feedback operation by receiving an input reference potential as a minus input and a feedback level received from the monitoring resistance element portion as a plus input. The current mirror amplifier judges whether the feedback level is higher or lower than the input reference potential. In response to the result of judgment, the output transistor controls an output reference potential to a predetermined target value. In case where the feedback level is higher than the input reference potential, the output reference potential is lowered and in case where the feedback level is lower than the input reference potential, the output reference potential is elevated. Thus, the output reference potential is controlled.
In a portion of the current mirror amplifier where the input reference potential and the feedback level is compared and judged and in the monitoring resistance element portion, an almost constant DC current always and continuously flows. The DC current occupies 20 to 40% of the self-refresh current corresponding to a standby current of the mobile DRAM.
The remaining part, i.e., 60 to 80% of the self-refresh current includes charging and discharging currents associated with the refresh operation and a defective leak current undesirably generated inside the mobile DRAM. As a matter of course, efforts are continued to reduce the remaining current accompanied with the refresh operation and the defective leak current. However, with respect to the DC current on which the present invention focuses attention, no discussion has been actively made because a ratio of the DC current with respect to the total self-refresh current is not so large as the present ratio of 20 to 40%.
At present, however, the reduction of the DC current is becoming a significant object. Specifically, the DC current of about 60 to 100 μA is desired to be reduced to a half or less, i.e., 30 to 50 μA.
Further, it is also an object to generate a stable output reference potential in the reference potential generating circuit. In the internal power supply potential supplying circuit of the above-mentioned Patent Document 1, even if the control signal SC1 is turned into an “H” level and the comparator is put into an active state, the comparator does not instantaneously perform a stable operation. Therefore, at the beginning of the active state of the comparator, the output reference potential of the internal power supply potential supplying circuit inevitably becomes unstable. The internal step-down power supply of the above-mentioned Patent Document 2 also has a comparator. Like in the internal power supply potential supplying circuit of the above-mentioned Patent Document 1, an output reference potential of the internal step-down power supply becomes unstable. The internal power supply voltage generating circuit of the above-mentioned Patent Document 3 also has a comparison circuit. Like in the internal power supply potential supplying circuit of the above-mentioned Patent Document 1, an output reference potential of the internal power supply voltage generating circuit becomes unstable.